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Minesh Patel

Seeking faculty positions in systems/computer architecture/dependability

Employment eligibility: US citizen

minesh.patelh@gmail.com
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Hi! I am a recent Ph.D. graduate (April 2022) in computer engineering from ETH Zürich, where I was advised by Onur Mutlu in the SAFARI research group. I am actively seeking a faculty position that will allow my work to influence both academia and industry by advancing the scientific state-of-the-art.


Research Interests

I am broadly interested in computer and systems architecture topics, including (1) architecture, compiler, and runtime support for workloads on cutting-edge systems; (2) system design, analysis, modeling, and evaluation; and (3) building dependable, safe, and secure systems. In general, I enjoy the challenge of exploring, developing, and/or demonstrating candidate solutions to loosely-defined problems.

My dissertation targets memory systems reliability — specifically, addressing DRAM technology scaling challenges, including DRAM refresh overheads and growing single-bit error rates. The dissertation contributes new techniques for understanding and identifying how errors manifest in modern DRAM chips, thereby enabling informed decision-making during system design. Here is a recent talk I delivered summarizing my dissertation work, for which I am honored to be awarded the William C. Carter PhD Dissertation Award in Dependability.

Beyond my dissertation, I have research experience in a broad range of topics related to the memory system, including rethinking hardware and/or software to enable new functionality (e.g., virtual memory abstractions, in-memory computation, security primitives) and improve system-level metrics such as performance, energy-efficiency, and security.


Education and Experience

I started my Ph.D. at Carnegie Mellon in 2015 and moved to ETH Zürich along with my adviser in 2017. Before that, I did my undergrad at UT Austin in both physics and electrical engineering.

I have substantial industry experience in the form of internships both before and during my Ph.D. During my Ph.D., I had (1) three research internships with Apple's Platform Engineering and SEG DRAM teams; and (2) one with Microsoft Research's Mobility and Networking Group. Before my Ph.D., I (1) worked with Apple's SEG Graphics team; (2) National Instruments R&D's Digital Design team; and (3) General Electric's UNIX/Linux Engineering team.


Awards


Publications

Please also see my Google Scholar page.

Refereed Conference Publications

  1. Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices

    G. Yaglikci, H. Luo, G. F. de Oliviera Jr., A. Olgun, Minesh Patel, J. Park, H. Hassan, J. S. Kim, L. Orosa, and O. Mutlu

    IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-52), Jun. 2022

  2. HARP: Practically and Effectively Identifying Uncorrectable Errors in Main Memory Chips That Use On-Die ECC

    Minesh Patel, G. F. de Oliveira Jr., O. Mutlu

    ACM Stamps for Full Artifact Evaluation

    International Symposium on Microarchitecture (MICRO-54), Oct. 2021

  3. A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

    L. Orosa, G. Yaglikci, H. Luo, A. Olgun, J. Park, H. Hassan, Minesh Patel, J. S. Kim, O. Mutlu

    International Symposium on Microarchitecture (MICRO-54), Oct. 2021

  4. QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

    Ataberk Olgun, Minesh Patel l, A. Giray Yaglikci, Haocong Luo, Jeremie S. Kim, F. Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, and Onur Mutlu

    International Symposium on Computer Architecture (ISCA-48), Jun. 2021

  5. CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations

    Lois Orosa, Yaohua Wang, Mohammad Sadrosadati, Jeremie S. Kim, Minesh Patel, Ivan Puddu, Haocong Luo, Kaveh Razavi, Juan Gomez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Saugata Ghose, and Onur Mutlu

    International Symposium on Computer Architecture (ISCA-48), Jun. 2021

  6. SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM

    Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, Joao Dinis Ferreira, Nika Mansouri Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gomez-Luna, and Onur Mutlu

    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-26), Mar.-Apr. 2021

  7. BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows

    A. G. Yaglikci, Minesh Patel, J. S. Kim, R. Azizi, A. Olgun, L. Orosa, H. Hassan, J. Park, K. Kanellopoulos, T. Shahroodi, S. Ghose, and O. Mutlu

    International Symposium on High-Performance Computer Architecture (HPCA-27), Feb. 2021

  8. Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

    Minesh Patel, J. S. Kim, T. Shahroodi, H. Hassan, and O. Mutlu

    International Symposium on Microarchitecture (MICRO-53), Oct. 2020

    Best Paper Award

  9. FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching

    Y. Wang, L. Orosa, X. Peng, Y. Guo, S. Ghose, Minesh Patel, J. S. Kim, J. G. Luna, M. Sadrosadati, N. M. Ghiasi, and O. Mutlu

    International Symposium on Microarchitecture (MICRO-53), Oct. 2020

  10. Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques

    J. S. Kim, Minesh Patel, A. G. Yaglikci, H. Hassan, R. Azizi, L. Orosa, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-47), Jun. 2020

  11. CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

    H. Luo, T. Shahroodi, H. Hassan, Minesh Patel, A. G. Yaglikci, L. Orosa, J. Park, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-47), Jun. 2020

  12. The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework

    N. Hajinazar, P. Patel, Minesh Patel, K. Kanellopoulos, S. Ghose, R. Ausavarungnirun, G. F. de Oliveira Jr., J. Appavoo, V. Seshadri, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-47), Jun. 2020

  13. Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers

    L. Cojocar, J. S. Kim, Minesh Patel, L. Tsai, S. Saroiu, A. Wolman, and O. Mutlu

    IEEE Symposium on Security and Privacy (S&P-41), May 2020

  14. CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability

    H. Hassan, Minesh Patel, J. S. Kim, A. G. Yaglikci, N. Vijaykumar, N. M. Ghiasi, S. Ghose, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-46), Jun. 2019

  15. CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators

    A. Boroumand, S. Ghose, Minesh Patel, H. Hassan, B. Lucia, R. Ausavarungnirun, K. Hsieh, N. Hajinazar, K. T. Malladi, H. Zheng, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-46), Jun. 2019

  16. Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices

    Minesh Patel, J. S. Kim, H. Hassan, and O. Mutlu

    IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-49), Jun. 2019

    Best Paper Award

  17. D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

    J. S. Kim, Minesh Patel, H. Hassan, L. Orosa, and O. Mutlu

    International Symposium on High-Performance Computer Architecture (HPCA-25), Feb. 2019

    IEEE Micro Top Picks Honorable Mention

  18. Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration

    Y. Wang, A. Tavakkol, L. Orosa, S. Ghose, N. M. Ghiasi, Minesh Patel, J. S. Kim, H. Hassan, M. Sadrosadati, and O. Mutlu

    International Symposium on Microarchitecture (MICRO-51), Oct. 2018

  19. Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines

    J. S. Kim, Minesh Patel, H. Hassan, and O. Mutlu

    IEEE International Conference on Computer Design (ICCD-36), Oct. 2018

  20. The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern DRAM Devices

    J. S. Kim, Minesh Patel, H. Hassan, and O. Mutlu

    International Symposium on High-Performance Computer Architecture (HPCA-24), Feb. 2018

  21. The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions

    Minesh Patel, J. S. Kim, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-44), Jun. 2017

Refereed Journal Publications

  1. LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory

    A. Boroumand, S. Ghose, Minesh Patel, H. Hassan, B. Lucia, K. Hsieh, K. T. Malladi, H. Zheng, and O. Mutlu

    IEEE Computer Architecture Letters (IEEE CAL), Jun. 2017

Ongoing Work

  1. A Case for Transparent Reliability in DRAM Systems

    Minesh Patel, T. Shahroodi, A. Manglik, G. Yaglikci, A. Olgun, H. Luo, and O. Mutlu

    arXiv, Apr. 2022

Doctoral Dissertation

  1. Enabling Effective Error Mitigation In Memory Chips That Use On-Die Error-Correcting Codes

    Minesh Patel

    Ph.D. Dissertation, ETH Zürich, Apr. 2022

    William C. Carter PhD Dissertation Award in Dependability


Talks

  1. Acceptance Speech: William C. Carter PhD Dissertation Award in Dependability

    Baltimore, MD, USA. Jun. 2022

    IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-52)

  2. HARP: Practically and Effectively Identifying Uncorrectable Errors in Main Memory Chips That Use On-Die ECC

    Virtual, Oct. 2021

    International Symposium on Microarchitecture (MICRO-54)

  3. Enabling Effective Error Mitigation in Memory Chips that Use On-Die Error-Correcting Codes

    Virtual, Sep. 2021

    SAFARI Live Seminar (website)

  4. Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

    Virtual, Oct. 2020

    International Symposium on Microarchitecture (MICRO-53)

  5. Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices

    Potland, OR, USA, Jun. 2019

    IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-49)

  6. The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions

    Toronto, Canada, Jun. 2017

    International Symposium on Computer Architecture (ISCA-44)